PCF8549 datasheet(11/36 Pages) PHILIPS

11 / 36 page

1997 Nov 21

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8549

RAM access

If the D/C bit is 1 the RAM can be accessed in both read

and write access mode, depending on the R/W bit. The

data is written to the RAM during the acknowledge cycle.

I2C-BUS INTERFACE

Characteristics of the I2C-bus

The I2C-bus is for bi-directional, two-line communication

between different ICs or modules. The two lines are a

serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

BIT TRANSFER (see Fig.9)

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during the HIGH

Fig.8 Read modify write access.

Set Address

Set Read

Modify Write Mode

Read Data

Write Data

END

Finished?

yes

period of the clock pulse as changes in the data line at this

time will be interpreted as a control signal.

START AND STOP CONDITIONS (see Fig.10)

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is

HIGH is defined as the STOP condition (P).

SYSTEM CONFIGURATION (see Fig.11)

• Transmitter: The device which sends the data to the bus

• Receiver: The device which receives the data from the

bus

• Master: The device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: The device addressed by a master

• Multi-Master: More than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: Procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronisation: Procedure to synchronize the clock

signals of two or more devices.

ACKNOWLEDGE (see Fig.12)

Each byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH signal put on the bus by

the transmitter during which time the master generates an

extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after

the reception of each byte. Also a master receiver must

generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The

device that acknowledges must pull-down the SDA line

during the acknowledge clock pulse, so that the SDA line

is stable LOW during the HIGH period of the acknowledge

related clock pulse (set-up and hold times must be taken

into consideration). A master receiver must signal an end

of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of

the slave. In this event the transmitter must leave the data

line HIGH to enable the master to generate a stop

condition.

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