PCF8531USLASH2 datasheet(18/44 Pages) PHILIPS

18 / 44 page

2000 Feb 11

Philips Semiconductors

Product speciﬁcation

× 128 pixel matrix driver

PCF8531

9I2C-BUS INTERFACE

9.1

Characteristics of the I2C-bus

The I2C-bus is for bi-directional, two-line communication

between different ICs or modules. The two lines are a

Serial Data line (SDA) and a Serial Clock line (SCL). Both

lines must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

9.1.1

BIT TRANSFER

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line

at this time will be interpreted as a control signal (see

Fig.10).

9.1.2

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P). The START

and STOP conditions are illustrated in Fig.11.

9.1.3

SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.12

• Transmitter: the device that sends the data to the bus

• Receiver: the device that receives the data from the bus

• Master: the device that initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-Master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

9.1.4

ACKNOWLEDGE

Acknowledge on the I2C-bus is illustrated in Fig.13. Each

byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH signal put on the bus by

the transmitter, during which time the master generates an

extra acknowledge related clock pulse. A slave receiver

that is addressed must generate an acknowledge after the

reception of each byte.

Also, a master receiver must generate an acknowledge

after the reception of each byte that has been clocked out

of the slave transmitter. The device that acknowledges

must pull-down the SDA line during the acknowledge clock

pulse so that the SDA line is stable LOW during the HIGH

period of the acknowledge- related clock pulse (set-up and

hold times must be taken into consideration). A master

receiver must signal an “end of data” to the transmitter by

not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event, the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition.

Fig.10 Bit transfer.

handbook, full pagewidth

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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