PCF85103C-2P datasheet(12/20 Pages) PHILIPS

12 / 20 page

2000 Feb 15

Philips Semiconductors

Product speciﬁcation

256

× 8-bit CMOS EEPROMs with

I2C-bus interface

PCF85102C-2; PCF85103C-2

11 I2C-BUS CHARACTERISTICS

All timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH

with an input voltage swing from VSS to VDD; see Fig.10; unless otherwise speciﬁed.

Note

1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be

internally provided by a transmitter.

12 WRITE CYCLE LIMITS

Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

fSCL

clock frequency

100

kHz

tBUF

bus free time between a STOP and START

condition

4.7

−µs

tHD;STA

START condition hold time after which ﬁrst clock

pulse is generated

4.0

−µs

tLOW

LOW-level clock period

4.7

−µs

tHIGH

HIGH-level clock period

4.0

−µs

tSU;STA

set-up time for START condition

repeated start

4.7

−µs

tHD;DAT

data hold time

for bus compatible masters

−µs

for bus devices

note 1

−

tSU;DAT

data set-up time

250

−

SDA and SCL rise time

−

µs

SDA and SCL fall time

−

300

tSU;STO

set-up time for STOP condition

4.0

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

E/W cycle timing

tE/W

E/W cycle time

internal oscillator

−

Endurance

NE/W

E/W cycle per byte

Tamb = −40 to +85 °C

100000

−−

cycles

Tamb =22 °C

−

1000000

−

cycles

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