1996 Nov 25

6

Philips Semiconductors

Product specification

PCF84C00

Table 2

PCF84C00T (see Fig.5)

SYMBOL

PIN

TYPE

DESCRIPTION

P2.2

1

I/O

1 bit of Port 2: 4-bit quasi-bidirectional I/O port

SDA/P2.3

2

I/O

quasi-bidirectional I/O port

SCLK

3

I/O

P0.0 to P0.1

4, 5

I/O

2 bits of Port 0: 8-bit quasi-bidirectional I/O port

DXALE

6

O

Address latch enable: on the falling edge of DXALE, the Dx address can be

latched in an external latch. This signal occurs only during execution of the

MOV Dx, A, MOV A, Dx, ANL Dx, A and ORL Dx, A instructions, with

x = 0 to 255. It is active during TS10 of cycle 1 and the first half of TS1 of

cycle 2.

n.c.

7

−

not connected

P0.2 to P0.7

8 to 13

I/O

6 bits of Port 0: 8-bit quasi-bidirectional I/O port

INT/T0

14

I

Interrupt/Test 0: external interrupt input (negative edge triggered)/test input

pin. When used as a test input, this pin is directly tested by conditional branch

instructions JT0 and JNT0; note 1.

T1

15

I

Test 1: test input pin, directly tested by conditional branch instructions JT1 and

JNT1. T1 may also be selected as an input to the 8-bit timer/event counter via

the STRT CNT instruction.

D0 to D2

16 to 18

I/O

3 bits of 8-bit data bus: for external memory and peripherals. The specified

Stop mode supply current is valid only if external pull-ups are connected to all

data lines.

A12

19

O

1 bit of 13-bit address bus: for external memory and peripherals

DXWR

20

O

Write strobe (active LOW): on the rising edge, data on D0-D7 may be written

to external registers. This signal occurs only during MOV Dx, A, ANL Dx, A

and ORL Dx, A instructions, with x = 0 to 255. It is active during TS7 of

cycle 2.

n.c.

21

−

not connected

A11 to A6

22 to 27

O

6 bits of 13-bit address bus: for external memory and peripherals

28

P

ground: circuit earth potential

A5 to A0

29 to 34

O

6 bits of 13-bit address bus: for external memory and peripherals

DXRD

35

O

Read strobe (active LOW): when this signal is active, external registers

emulating Dx registers can be read by the data bus. This signal occurs only

during execution of MOV A, Dx, ANL Dx, A and ORL Dx, A instructions, with

x=0to 255. It is active during TS3 and TS4 of cycle 2.

D3 to D7

36 to 40

I/O

5 bits of 8-bit data bus: for external memory and peripherals. The specified

Stop mode supply current is valid only if external pull-ups are connected to all

data lines.

PSEN

41

O

Program store enable (active LOW): PSEN is used to enable external

program memory and is active during TS9 and TS10 of each machine cycle

and TS1 of each following cycle. PSEN is HIGH during the Stop mode.

XTAL1

42

I

oscillator input: input from a crystal which determines the internal oscillator

frequency or an external clock generator

XTAL2

43

I/O

oscillator output: output of the inverting amplifier