PCF5078 datasheet(4/20 Pages) PHILIPS

4 / 20 page

1999 Apr 12

Philips Semiconductors

Product speciﬁcation

Power ampliﬁer controller for GSM and

PCN systems

PCF5078

PINNING

FUNCTIONAL DESCRIPTION

General

The PCF5078 integrates an amplifier for the detected RF

voltage from the sensor, an integrator and an active filter

to build a PA control loop with a small amount of passive

components.

The sensor amplifier is able to amplify signals from a RF

power detector in a range of

−20 to +15 dBm. This

complies to the PA output power range of GSM and PCN

systems when a directional coupler with 20 dB attenuation

is used.

The Schottky diode for power detection (sensor) is biased

by an integrated current source of 30

µA. Variations of the

forward voltage of the diodes with the temperature have no

influence on the measured signal, because they are

cancelled by sampling around the switched capacitor

operational amplifier OP1 (see Fig.1).

SYMBOL

DESCRIPTION

PA control output voltage

VINT

negative integrator input

VS1

sensor signal input 1

VS2

sensor signal input 2

VSS

ground supply

VDAC

DAC input voltage

VHOME

home position input voltage

VDD

supply voltage

Fig.2 Pin configuration.

handbook, halfpage

MGS194

PCF5078

VDD

VDAC

VINT

VHOME

VSS

VS2

VS1

An external Digital-to-Analog Converter (DAC) with10-bit

resolution is necessary to control the loop e.g. the

AUXDAC3 of the baseband interface family PCF5073x.

An integrated active filter smooths the voltage steps of the

DAC and avoids a feedthrough of the DAC harmonics into

the modulation spectra of the PA.

The DAC signal and the sensor signal are added by

operational amplifier OP1. The voltage difference of both

signals is integrated by operational amplifier OP4, which

provides the PA control voltage on pin VC. The integration

is performed by means of an external capacitance CVINT

connected between pins VINT and VC.

The shape of the rising and falling power burst edges can

be determined by means of the DAC voltage (see Fig.3).

Power-down mode

During the not used time slots in Time Division Multiple

Access (TDMA) systems, the PCF5078 must be turned off

by switching off the supply voltage on pin VDD.

Initial conditions and start-up

The PCF5078 has been designed to operate in bursts as

required in TDMA systems. For each time slot to be

transmitted it must be powered-up by switching on the

supply voltage. This allows a proper initialization of

switches S1 to S5.

During start-up switches S1, S2 and S3 are closed and

switches S4 and S5 are opened (see Fig.4).

The forward voltages on the Schottky diodes are sampled

on capacitors C1 and C2, respectively, because switch S1

is closed. Moreover, the control voltage on pin VC is

initially forced to pre-bias level Vprebias because

switches S2 and S3 are closed and switch S4 is opened.

Switch S1 is opened after a fixed time the supply voltage

has been switched on and then the circuit is ready. This

time is defined on-chip and can be maximum 45

µs. Once

switch S1 is open, a ramp signal with a minimum

amplitude of 25 mV applied on pin VDAC determines

opening of switch S3 and closing of switch S4 with a delay

of maximum 3

µs with respect to the start of the ramp.

After opening switch S3, the control voltage on pin VC

rises in a fixed amount of time to the home position level

so biasing the PA to the beginning of the active range of its

control curve. Switch S2 remains closed during this typical

time of 2

µs. When switch S2 is opened, switch S5 is

closed allowing the transfer of any signal coming from

amplifier OP1.

PCF5078 датащи(PDF) 4 Page - NXP Semiconductors

PCF5078 датащи(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL