1997 Nov 19

8

Philips Semiconductors

Preliminary specification

Power amplifier controller for GSM and

PCN systems

PCF5077T

Serial bus programming

A simple 3-wire unidirectional serial bus is used to program

the circuit. The 3 wires are DATA, CLK and STROBE.

The data sent to the device is loaded in bursts framed by

STROBE. Programming clock edges and their appropriate

data bits are ignored until STROBE goes active LOW.

The last four address bits are decoded on the active

STROBE edge. This produces an internal load pulse to

store the data in one of the addressed registers. To avoid

erroneous circuit operation, the STROBE pulse is not

allowed during internal data reads by the rest of the circuit.

This condition is guaranteed by respecting a minimum

STROBE pulse width after data transfer.

Only the last 16 bits serially clocked into the device are

retained within the programming register. Additional

leading bits are ignored, and no check is made on the

number of clock pulses. The fully static CMOS design uses

virtually no current when the bus is inactive. The bus is

also programmable during power-down.

Data format

Data is entered with the most significant bit (MSB) first.

The leading 10 bits p15 to p6 are the data field, the

following bits p5 and p4 form the subaddress, while the

last 4 bits p3 to p0 are the device address field.

The PCF5077T uses only one of the available addresses.

The format is given in Table 2.

The correspondence between data and address fields is

given in Table 3 and the description in Table 4.

All three registers in Table 3 are set to 00H during reset.

Table 2

Programming register format

Table 3

Register bit allocation

Table 4

Description of bits used in Table 3

DATA BITS

SUBADDRESS

DEVICE ADDRESS

MSB

LSB

p15

p14 to p8

p7

p6

p5

p4

p3

p2

p1

p0

data9

data8 to data2

data1

data0

Sadd1

Sadd0

add3

add2

add1

add0

DATA FIELD (D9 TO D0)

SUBADDRESS

DEVICE ADDRESS

MSB

LSB

p15

p14

p13

p12

p11

p10

p9

p8

p7

p6

p5

p4

p3

p2

p1

p0

Vk5

Vk4

Vk3

Vk2

Vk1

Vk0

Lim1

Lim0

DC

Test

0

0

1

0

1

0

Vh5

Vh4

Vh3

Vh2

Vh1

Vh0

DVh1 DVh0

DR1

DR0

0

1

1

0

1

0

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

DF1

DF0

1

1

1

0

1

0

BITS

DESCRIPTION

Vk5 to Vk0

6 bits to control the kick voltage in 64 steps

Vh5 to Vh0

6 bits to control the home position voltage in 64 steps

PL7 to PL0

8 bits to control the power level in 256 steps

Lim1 and Lim0

2 bits to control the limiter voltage (see Table 5)

DC

direct control with ramping function (control loop is switched off when DC = 1)

Test

test mode (Test = 1); must always be set to logic 0 in application

DVh1 and DVh0

DR1

gain factor of OP1

DR0

gain factor for slope generator output

DF1

enable of the 3-state output on pin DF (for DF1 = 0, pin DF is in 3-state mode)

DF0

data output on pin DF