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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F276 датащи(PDF) 108 Page - STMicroelectronics |
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ST10F276 датащи(HTML) 108 Page - STMicroelectronics |
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108 / 229 page  System reset ST10F276 108/229 Figure 25. Asynchronous power-on RESET (EA = 0) Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 37, 38 and 39. It occurs when RSTIN is low and RPD is detected (or becomes) low as well. RSTIN P0[15:13] P0[12:2] not t. transparent not t. P0[1:0] not t. not transparent V18 XTAL1 ... 3..8 TCL1) RST Latching point of Port0 for system start-up configuration VDD ≥ 1 ms (for on-chip VREG stabilization) RPD ALE ≥ 1.2 ms (for resonator oscillation + PLL stabilization) ≥ 10.2 ms (for crystal oscillation + PLL stabilization) Note 1. 3 to 8 TCL depending on clock source selection. RSTF ≤ 500 ns (After Filter) ≥ 50 ns 8 TCL transparent 3..4 TCL |
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