PCD6001 datasheet(26/96 Pages) PHILIPS

26 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6001

10.4

Microcontroller interrupts

The microcontroller has 15 interrupt sources, shown

below, which can be programmed to have a low or high

priority. If enabled these interrupts sources result in jump

to the addresses shown in Table 14.

• EX2 to EX6 asynchronous external interrupts via

P1.0 to P1.4

• EX0 and EX1 asynchronous external interrupts via

P3.2 (INT0N) and P3.3 (INT1N)

• DSP_event

• FS_event

• TIME_event

• I2C-bus interrupt

• RTC_event

• Timer 0 and Timer 1 interrupt

• MSK interrupt.

The external interrupt configuration of P1 is shown in

Fig.9. Pins P1.5, P1.6 and P1.7 cannot be used as

external interrupts. The IX1 SFR determines the polarity of

the external interrupt sources of P1. Clearing the ‘global

enable’ bit in IEN0 disables all interrupt sources. Using

IEN0 (and IEN1) each individual external interrupt can be

enabled or disabled.

The IRQ1 SFR stores all external interrupts. So if an

external interrupt with a low priority is detected during

execution of another (high or low priority) interrupt it will be

handled just after the return of this interrupt.

The interrupt service routine for an external interrupt must

clear the right IRQ1 flag to indicate that it has serviced the

interrupt request. Notice that during the interrupt routine

this flag can be set again immediately after clearing the

IRQ1 flag if the interrupt source is (still) HIGH.

The complete interrupt system is shown in Fig.10. All

15 interrupts are allocated and can be given a low or high

priority according to the setting of IP0 and IP1.

Each interrupt source can be individually enabled by

means of IEN0 and IEN1.

The IRQ1 and IX.7 registers are clocked (a clock which is

active during Idle) and can be set by P1.0 to P1.4, the

TIME_event, the DSP_event, the FS_event and the

RTC_event. These flags can only be cleared by software.

Only TCON.1, TCON.3, TCON.5 and TCON.7 flags are

cleared by the interrupt controller hardware. All other flags

must be cleared by software.

The polling of a potential interrupt goes from a high priority

to a low priority interrupt. Within a high (or low) priority

interrupt level the EX0 (if set to high priority) will be polled

first followed by the next high priority interrupt.

The interrupt SFRs IP0, IP1, IEN0, IEN1, IRQ1 and IX1 are

defined in Sections 10.4.1 to 10.4.6. A flag set to logic 1 in

IP0 or IP1 (Tables 15 and 16) causes the corresponding

interrupt to have high priority.

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