Data Sheet

ADPA1113

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 17

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 7

NIC

No Internal Connection. The NIC pins are not connected internally. For normal operation, connect to ground.

2

VDD1

Drain Bias for First Stage of Amplifier. See Figure 3 for the VDD1 pin interface schematic.

3, 5, 10, 12

GND

Ground. The ground pins must be connected to the RF and the DC ground. See Figure 4 for the GND interface schematic.

4

RFIN

RF Input. The RFIN pin is AC-coupled and internally matched to 50 Ω. See Figure 3 for the RFIN interface schematic.

6

VGG1

Gate Control for All Three Stages of the Amplifier. See Figure 3 for the VGG1 interface schematic.

8

VDD2B

Drain Bias for the Second Stage of the South Side of the Amplifier. See Figure 5 for the VDD2B interface schematic.

9

VDD3B

Drain Bias for the Third Stage of the South Side of the Amplifier. See Figure 6 for the VDD3B interface schematic.

11

RFOUT

RF Output. The RFOUT pin is AC-coupled and internally matched to 50 Ω. See Figure 6 for the RFOUT interface schematic.

13

VDD3A

Drain Bias for the Third Stage of the North Side of the Amplifier. See Figure 6 for the VDD3A interface schematic.

14

VDD2A

Drain Bias for the Second Stage of the North Side of the Amplifier. See Figure 5 for the VDD2A interface schematic.

Package Base

GND

The package base must be connected to the RF and the DC ground. See Figure 4 for the GND Interface schematic.