PCD5041 datasheet(9/28 Pages) PHILIPS

9 / 28 page

1996 Oct 31

Philips Semiconductors

Objective speciﬁcation

DECT burst mode controller

PCD5041

FUNCTIONAL DESCRIPTION (see Fig.1)

The PCD5041 has dedicated hardware blocks containing

logic for time-critical functions requiring bit or byte-time

accuracy. Other functions requiring only slot-time

accuracy are performed by software in the Programmable

Communication Controller (PCC). This approach offers

maximum flexibility during prototyping.

6.1

Internal bus and data memory

6.1.1

INTERNAL BUS

The function of the internal bus is:

• To provide access for all functional blocks to the

common data memory

• To provide access for the microcontroller-interface and

the PCC to all other functional blocks.

All functional blocks (speech-interface, RF-interface,

microcontroller-interface and PCC) can autonomously use

the internal bus to communicate with the common data

memory.

A bus controller is used to handle the bus priority

mechanism. When several blocks request access

simultaneously, the request with the highest priority is

handled first.

6.1.2

DATA MEMORY

A large part of the data memory is used for the bit rate

adaptation between the DECT radio interface and the

speech interface. The data memory also acts as the main

communication interface between the external

microprocessor and the PCC.

In a handset, the device uses only 1 kbyte of the common

data memory. The remaining 1 kbyte can be used by the

microcontroller as an extended data memory for the higher

layer software. The microcontroller is not aware of the fact

that it is sharing the memory with the PCD5041. From the

microcontroller’s point of view, the PCD5041’s

microcontroller-interface plus the common data memory

behave as a standard RAM device.

6.2

Clock generation and correction (see Fig.4)

The device has an on-chip 13.824 MHz crystal oscillator.

From this source, a few frequencies are derived for internal

and external use. Frequencies generated for external use

are:

• 13.824 MHz for the synthesizer reference

(pin REF_CLK). This output is only provided if the

synthesizer power-down control (output on

pin S_POWER_DWN) is not selected.

• 0.144 to 13.824 MHz for the microcontroller clock

(pin PROC_CLK)

• 3.456 MHz for the ADPCM CODEC (pin CLK3)

• 1200 Hz (pin 1200_HZ) for dual synthesizer switching

• 100 Hz (pin CLK100) indicates start of frame.

Nominally, the frequency on pin CLK3 is 3.456 MHz. This

frequency is obtained by dividing the crystal frequency by

4. Sometimes, the crystal frequency will be divided by 3

or by 5, to synchronize the combination of the ADPCM

CODEC and the device to an external source. For the

handset application, the PCD5041 can be synchronized to

the incoming radio channel, using the ‘slot

synchronization’ event of one active channel, so the

handset is locked to one base station.

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