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AS8S128K32P-17/883C датащи(PDF) 3 Page - Austin Semiconductor |
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AS8S128K32P-17/883C датащи(HTML) 3 Page - Austin Semiconductor |
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3 / 12 page ![]() SRAM SRAM SRAM SRAM SRAM AS8S128K32 Austin Semiconductor, Inc. AS8S128K32 Rev. 4.0 5/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 AC TEST CONDITIONS TEST SPECIFICATIONS Input pulse levels........................................VSS to 3V Input rise and fall times..........................................5ns Input timing reference levels.................................1.5V Output reference levels........................................1.5V Output load.............................................See Figures 1 TRUTH TABLE MODE OE\ CE\ WE\ I/O POWER Read L L H Q ACTIVE Write X L L D ACTIVE Standby X H X HIGH Z STANDBY Not Selected H L H HIGH Z ACTIVE OH OL I I Current Source Current Source Vz = 1.5V (Bipolar Supply) Device Under Test Ceff = 50pf -+ + NOTES: Vz is programable from -2V to + 7V. I OL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of V OH and VOL. I OL and IOH are adjusted to simulate a typical resistive load circuit. SYMBOL PARAMETER MAX UNITS NOTES CADD A0 - A18 Capacitance 40 pF 4 COE OE\ Capacitance 40 pF 4 CWE, CCE WE\ and CE\ Capacitance 20 pF 4 CIO I/O 0- I/O 31 Capacitance 20 pF 4 Figure 1 CAPACITANCE TABLE (V IN = 0V, f = 1 MHz, TA = 25 oC) |
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