PCD5003AH datasheet(13/44 Pages) PHILIPS

13 / 44 page

1999 Jan 08

Philips Semiconductors

Product speciﬁcation

Enhanced Pager Decoder for POCSAG

PCD5003A

Table 9

Call terminator bit identiﬁcation

Note

1. The DF bit in the call terminator is set:

a) When any call data code-word in the terminating batch was uncorrectable, while in ‘data receive’ mode.

b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a

user-programmed sync word, while in ‘data fail’ mode.

Table 10 Error type identiﬁcation (note 1)

Note

1. POCSAG code allows a maximum of three bit errors to be detected per code-word.

BITS (MSB TO LSB)

IDENTIFICATION

forced call termination (1 = yes)

S3 to S1

identifier number of last sync word

data fail mode indication (1 = data fail mode); note 1

E3 to E1

detected error type; see Table 10; E3 = 0 in a call terminator

ERROR TYPE

NUMBER OF ERRORS

no errors; correct code-word

parity bit in error

single bit error

1 + parity

single bit error and parity error

not used

4-bit burst error and parity error

3 (e.g. 1101)

2-bit random error

uncorrectable code-word

3 or more

Call termination can occur on reception of an address

code-word (or even a message code-word if in enhanced

call termination mode) or when a sync word is not detected

while in the ‘data fail’ mode.

7.19

Receiver and oscillator control

A paging receiver and an RF oscillator circuit can be

controlled independently via enable outputs RXE and ROE

respectively. Their operating periods are optimized

according to the synchronization mode of the decoder.

Each enable signal has its own programmable

establishment time (see Table 11).

7.20

External receiver control and monitoring

An external controller may enable the receiver control

outputs continuously via an I2C-bus command, overruling

the normal enable pattern. Data reception continues

normally. This mode can be left by means of a reset or an

I2C-bus command.

External monitoring of the receiver control output RXE is

possible via bit D6 in the status register, when enabled via

the control register (D2 = 1). Each change of state of

output RXE will generate an external interrupt at output

INT.

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