PCD5003A datasheet(8/44 Pages) PHILIPS

8 / 44 page

1999 Jan 08

Philips Semiconductors

Product speciﬁcation

Enhanced Pager Decoder for POCSAG

PCD5003A

Table 1

POCSAG recommended call types and function bits

7.3

Error correction

Table 2

Error correction

BIT 20 (MSB)

BIT 21 (LSB)

CALL TYPE

DATA FORMAT

numeric

4-bits per digit

alert only 1

−

alert only 2

−

alphanumeric

7-bits per ASCII character

ITEM

DESCRIPTION

Preamble

4 random errors in 31 bits

Synchronization code-word

2 random errors in 32 bits

Address code-word

2 random errors; plus 4-bit burst errors (optional)

Message code-word

2 random errors; plus 4-bit burst errors (optional)

7.4

Operating states

The PCD5003A has 2 operating states:

• ON status

• OFF status.

The operating state is determined by a Direct Control input

(DON) and bit D4 in the control register (see Table 3).

Table 3

Truth table for decoder operating status

7.5

ON status

In ON status the decoder pulses the receiver and oscillator

enable outputs (respectively RXE and ROE) according to

the code structure and the synchronization algorithm. Data

received serially at the data input (RDI) is processed for

call receipt. Reception of a valid paging call is signalled to

the microcontroller by means of an interrupt signal.

The received address and message data can then be read

via the I2C-bus interface.

DON INPUT

CONTROL

BIT D4

OPERATING

STATUS

OFF

7.6

OFF status

In OFF status the decoder will neither activate the receiver

or oscillator enable outputs, nor process any data at the

data input. The crystal oscillator remains active to permit

communication with the microcontroller.

In both operating states an accurate timing reference is

available via the REF output. By SPF programming the

signal periodicity may be selected as 32.768 kHz, 50 Hz,

2Hzor 1

⁄60 Hz.

7.7

Reset

The decoder can be reset by applying a positive pulse on

input pin RST. A power-on reset circuit consisting of an

RC network can be connected to this input as well.

Conditions during and after a reset are described in

Chapter “Operating instructions”.

For successful reset at power-on, a HIGH level must be

present on the RST pin while the device is powering-up.

This can be applied by the microcontroller, or via a suitable

RC power-on reset circuit connected to the RST input.

Reset circuit details and conditions during and after a reset

are described in Chapter 8.

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