PCD5002AH datasheet(21/48 Pages) PHILIPS

21 / 48 page

1999 Jan 08

Philips Semiconductors

Product speciﬁcation

Enhanced Pager Decoder for

APOC1/POCSAG

PCD5002A

Table 16 Index register

Notes

1. The index register only uses the least significant nibble, the upper 4 bits are ignored.

2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.

ADDRESS(1)

ACCESS

00H

status

00H

control

01H

real-time clock: seconds

R/W

02H

real-time clock: 1

⁄100 second

R/W

03H

alert cadence

04H

alert set-up

05H

periodic interrupt modulus

05H

periodic interrupt counter

06H

RAM write address pointer

07H

EEPROM address pointer

R/W

08H

RAM read address pointer

R/W

09H

RAM data output

0AH

EEPROM data input/output

R/W

0BH to 0FH

unused

note 2

8.28

External interrupt

The PCD5002A can signal events to an external controller

via an interrupt signal at output INT. The interrupt polarity

is programmable via SPF programming. The interrupt

source is shown in the status register.

Interrupts are generated by the following events (more

than one event is possible):

• Call data available for output (bit D2)

• SRAM pointers becoming equal (bit D3)

• Expiry of periodic time-out (bit D7)

• Expiry of alert time-out (bit D4)

• Change of state in out-of-range indicator (bit D5)

• Change of state in battery-low indicator or in receiver

control output RXE (bit D6).

Immediate interrupts are generated by status bits D3,

D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6

(BAT monitoring) generate interrupts as soon as the

receiver is disabled (RXE = 0).

When call data is available (D2 = 1) but the receiver

remains switched on, an interrupt is generated at the next

sync word position, if data fail mode (short fade recovery

mode in APOC1) is not active.

The interrupt output INT is reset after completion of a

status read operation.

8.29

Interrupt masking

In the PCD5002A certain interrupts can be suppressed by

masking via the control register. The following interrupts

can be masked:

• Out-of-Range (status bit D5): change of state

interrupt, masked by setting control register bit D5

• BAT/RXE monitoring (status bit D6): change of state

interrupt (source selected by control register bit D2),

masked by setting control register bit D6

• Periodic Timer (status bit D7): timer overflow interrupt,

masked by setting control register bit D7.

Although no interrupts are generated by these conditions

when masked via the control register, the corresponding

status bits are updated normally and available via the

status register. At reset the control register is cleared,

causing all interrupts to be enabled.

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