DRAM

DRAM

DRAM

DRAM

DRAM

AS4LC4M16

Austin Semiconductor, Inc.

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

1

AS4LC4M16

Rev. 1.0 7/02

4 MEG x 16 DRAM

Extended Data Out (EDO) DRAM

FEATURES

• Single +3.3V ±0.3V power supply.

• Industry-standard x16 pinout, timing, functions, and

package.

• 12 row, 10 column addresses

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• Extended Data-Out (EDO) PAGE MODE access

• 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH

distributed across 64ms

• Optional self refresh (S) for low-power data retention

• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020

OPTIONS

MARKINGS

• Package(s)

50-pin TSOP (400-mil)

DG

• Timing

50ns access

-5

60ns access

-6

• Refresh Rates

Standard Refresh

None

Self Refresh

S*

• Operating Temperature Ranges

Military (-55°C to +125°C)

XT

Industrial (-40°C to +85°C)

IT

NOTE: The \ symbol indicates signal is active LOW.

*Contact factory for availability. Self refresh option available on IT

version only.

For more products and information

please visit our web site at

www.austinsemiconductor.com

PIN ASSIGNMENT

(Top View)

50-Pin TSOP (DG)

Configuration

4 Meg x 16

Refresh

4K

Row Address

A0-A11

Column Addressing

A0-A9

SPEED

-5

84ns

50ns

20ns

25ns

13ns

8ns

-6

104ns 60ns

25ns

30ns

15ns

10ns

KEY TIMING PARAMETERS