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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9898 датащи(PDF) 21 Page - Analog Devices |
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AD9898 датащи(HTML) 21 Page - Analog Devices |
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21 / 52 page  REV. 0 AD9898 –21– Table IX. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE RG Rising Edge RG Falling Edge Signal Name Quadrant (Not Programmable) RGNEGLOC Quadrant Range RG I Fixed at 000000 000000 to 001011 P[0] to P[11] II Fixed at 000000 010000 to 011011 P[12] to P[23] III Fixed at 000000 100000 to 101011 P[24] to P[35] IV Fixed at 000000 110000 to 111011 P[36] to P[47] H1 Rising Edge H1 Falling Edge Signal Name Quadrant H1POSLOC Quadrant Range (Not Programmable) H1 I 000000 to 001011 P[0] to P[11] H1POSLOC + 24 Steps II 010000 to 011011 P[12] to P[23] H1POSLOC + 24 Steps III 100000 to 101011 P[24] to P[35] H1POSLOC + 24 Steps IV 110000 to 111011 P[36] to P[47] H1POSLOC + 24 Steps cds Rising Edge cds Falling Edge Signal Name Quadrant SHPLOC Quadrant Range SHDLOC Quadrant Range cds I 000000 to 001011 P[0] to P[11] 000000 to 001011 P[0] to P[11] II 010000 to 011011 P[12] to P[23] 010000 to 011011 P[12] to P[23] III 100000 to 101011 P[24] to P[35] 100000 to 101011 P[24] to P[35] IV 110000 to 111011 P[36] to P[47] 110000 to 111011 P[36] to P[47] Data Output[9:0] Rising Edge Data Output[9:0] Falling Edge Signal Name Quadrant DOUTPHASE Quadrant Range (Not Programmable) Data Output[9:0] I 000000 to 001011 P[0] to P[11] DOUTPHASE + 24 Steps II 010000 to 011011 P[12] to P[23] DOUTPHASE + 24 Steps III 100000 to 101011 P[24] to P[35] DOUTPHASE + 24 Steps IV 110000 to 111011 P[36] to P[47] DOUTPHASE + 24 Steps Signal Name DCLKPHASE Value DCLKPHASE Rising Edge DCLKPHASE Falling Edge DCLK1 00 P[6] P[26] 01 P[16] P[36] 10 P[26] P[06] 11 P[36] P[16] Table VIII. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters Register Name Bit Width Register Type Range Description RGNEGLOC 6 Control (Addr 0x03) 0–47 Edge Location Falling Edge Location for RG H1POSLOC 6 Control (Addr 0x03) 0–47 Edge Location Positive Edge Location for H1 SHPLOC 6 Control (Addr 0x02) 0–47 Edge Location Sample Location for SHP SHDLOC 6 Control (Addr 0x02) 0–47 Edge Location Sample Location for SHD DOUTPHASE 6 Control (Addr 0x02) 0–47 Edge Location Phase Location of Data Output [9:0] DCLKPHASE 6 Control (Addr 0x02) 0–47 Edge Location Positive Edge of DCLK 1 The 2 MSB are used to select the quadrant. |
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