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MLA537

PORT 0

FLIP-FLOP

PORT 0

BUFFER

HIGHER

PROGRAM

COUNTER

LOWER

PROGRAM

COUNTER

PROGRAM

STATUS

WORD

MEMORY

BANK

FLIP-FLOPS

6 kbytes

(PCD3353C; 53A)

4 kbytes

(PCD3352C; 52A)

2 kbytes

(PCD3351C; 51A)

128 bytes

(PCD3352C; 52A; 53C; 53A)

64 bytes

(PCD3351C; 51A)

DECODE

RESIDENT ROM

58

8

8

8

P0.0 to P0.7

8

8

88

8

8

TIMER/

EVENT

COUNTER

32

INTERNAL

CLOCK

FREQ.

30

T1

PORT 1

BUFFER

PORT 1

FLIP-FLOP

P1.7/MDY P1.0 to P1.6

8

PORT 2

BUFFER

PORT 2

FLIP-FLOP

P2.0 to P2.3

4

4

7

8

MELODY

CONTROL

REGISTER

8

TONE

FILTER

OSCILLATOR

RAM

ADDRESS

REGISTER

ACCUMULATOR

TEMPORARY

REGISTER 1

TEMPORARY

REGISTER 2

ARITHMETIC

DECIMAL

ADJUST

CONTROL AND TIMING

XTAL2

XTAL1

RESET

CE/T0

STOP

IDLE

INTERRUPT

INITIALIZE

MULTIPLEXER

8 LEVEL STACK

(VARIABLE LENGTH)

OPTIONAL SECOND

REGISTER BANK

DATA STORE

D

E

C

O

D

E

REGISTER 0

REGISTER 1

REGISTER 2

REGISTER 3

REGISTER 4

REGISTER 5

REGISTER 6

REGISTER 7

timer interrupt

external interrupt

RESIDENT RAM ARRAY

derivative

interrupt

8

LOGIC UNIT

8

INSTRUCTION

REGISTER

AND

DECODER

CONDITIONAL

BRANCH

LOGIC

CE/T0

TIMER

FLAG

CARRY

ACC

ACC BIT

TEST

T1

LGF

REGISTER

8

HGF

REGISTER

8

SINE WAVE

GENERATOR

INTERRUPT

LOGIC

8

EEPROM

DATA

TRANSFER

8

EEPROM

ADDRESS

REGISTER

8

EEPROM

CONTROL

REGISTER

8

TIMER 2

REGISTER

8

TIMER 2

RELOAD

REGISTER

8

EEPROM

PCA3351C

PCA3352C

PCA3353C

PCD3351A

PCD3352A

PCD3353A

POWER-ON-RESET

VPOR

RESET

Fig.1 Block diagram.