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CYPAP211 датащи(PDF) 4 Page - Infineon Technologies AG

номер детали CYPAP211
подробное описание детали  EZ-PD™ PAG2P primary-side startup controller
PDF  27 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYPAP211 датащи(HTML) 4 Page - Infineon Technologies AG

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Datasheet
4
002-34772 Rev. *F
2023-06-13
EZ-PD™ PAG2P primary-side startup controller
Pinout
1Pinout
Figure 1
Pin map (SOIC-14)
Table 1
EZ-PD™ PAG2P pin description
Pin number
Pin name
Description
1HV
High voltage start-up power supply input. HV is the power supply source during the
start-up phase. This pin can be connected to either the bridge rectifier output or
directly to the AC mains through the diodes. This pin has a maximum voltage rating
of 500 V.
2,3
NC
No connect
4GDH
High-side gate driver logic signal output. This pin is connected to high side FET via
external high-side floating driver IC
5PULSEIN Pulse edge transformer (PET) input. EZ-PD™ PAG2P synchronizes to the secondary
side pulses received at the PULSEIN input.
6SS
External soft-start ramp capacitor terminal. This pin connects to the other end of
the pulse transformer. The external capacitor connected to the SS pin determines
the soft-start time.
7RT
External timing resistor or bias current source. The RT pin is used to connect to an
external timing resistor of 50 kΩ which determines the free running oscillator
frequency. Oscillator frequency is typically 30 kHz.
8GND
Ground
9CS
Current sense input. Current sense input is used to provide overcurrent or
short-circuit protection. Protection is provided by two current sense thresholds,
CSTH1 (pulse by pulse) and CSTH2 (Short circuit) in the primary side by turning OFF
the primary FET.
10
GDL
Primary FET low-side gate driver signal
11
VCC
Low voltage power supply input
12
BSW
Boost converter switch node connected to drain terminal of internal HV NFET. This
pin is connected to external boost inductor and diode.
13
BGND
Boost converter return pin connected to source terminal of internal HV NFET. This
pin is connected to GND.
14
OVP_AUX
Auxiliary winding overvoltage detection input. EZ-PD™ PAG2P monitors this pin for
overvoltage condition of secondary side, using an external resistor divider. Any
voltage exceeding V_OVPAUXRISE on this pin is treated as an overvoltage fault
condition. The overvoltage condition is monitored only during startup or open
loop operation.
HV
1
NC
2
NC
3
GDH
4
PULSEIN
5
SS
6
RT
7
OVP_AUX
14
BGND
13
BSW
12
VCC
11
GDL
10
CS
9
GND
8



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