UCD7230PWPR datasheet(7/33 Pages) TI

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UCD7230

SLUS741C – NOVEMBER 2006 – REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS (continued)

DD = PVDD = 12 V, 4.7-µF from VDD to AGND, 1 µF from PVDD to PGND, 0.1 µF from CSBIAS to AGND, 0.22 µF from BST to

SW, T

A = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise

noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT SENSE COMPARATOR (INPUT SENSE)

RDLY = 24.3 kΩ (CSBIAS-CS+)

170

235

300

CS threshold

RDLY = 49.9 kΩ (CSBIAS-CS+)

114

140

RDLY = 24.3 kΩ , IN rising to OUT1,

120

IN falling to OUT2, VDD = 6 V

CS blanking time(2)

RDLY = 49.9 kΩ , IN rising to OUT1,

230

IN falling to OUT2, VDD = 6 V

RDELAY range(2)

24.3

50.0

100.0

Ω

Propagation delay from CS+ to

OUT1(2)

CS = threshold + 60mV

Propagation delay from CS+ to

CLF(2)

CURRENT SENSE AMP

I0 = OPEN; POS = NEG = 1.25 V;

VOO

Output offset voltage

-100

100

measure AO - IO

I0 = FLOAT; VPOS = 1.26 V; VNEG =

Closed loop dc gain

V/V

1.25 V, RPOS = RNEG = 0

POS = 1.25 V, NEG = 1.29 V,R =

Input impedance

5.5

8.3

Ω

(POS - NEG) / (IPOS - INEG)

VCM(max) is limited to (VDD-1.2V),

VCM

Input Common Mode Voltage Range

5.6

RPOS = 0

VPOS = 1.2 V; VNEG = 1.3 V;

A0_Vol

Minimum Output Voltage

0.15

0.3

A0_ISINK = 250 µA

VPOS =1.3 V; VNEG = 1.2 V; A0_

A0_Voh

Maximum Output Voltage

3.1

3.5

ISOURCE = 500 µA

I0 = FLOAT; VPOS = VNEG = 0.8 V to

Input Bias Current, POS or NEG

-2

µA

5.0 V, RPOS = RNEG = 0

ZERO CURRENT REFERENCE (IO)

Reference voltage

Measured at I0

0.54

0.6

0.66

Input transition voltage

With respect to IO reference

120

Output impedance

IZERO = 0.6 V

Ω

(2)

As designed and characterized. Not 100% tested in production.

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