UCD7230 datasheet(9/33 Pages) TI

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DEVICE INFORMATION

UCD7230

SLUS741C – NOVEMBER 2006 – REVISED MARCH 2007

TERMINAL FUNCTIONS

TERMINAL

UCD7230

I/O

DESCRIPTION

NAME

HTSSOP-

QFN-20

Supply input pin to power the internal circuitry except the driver outputs. The

VDD

UCD7230 accepts an input range of 4.5 V to 15.5 V.

Synchronous Rectifier Enable. The SRE pin is a high impedance digital input

capable of accepting 3.3-V logic level signals, used to disable the synchronous

SRE

rectifier switch. The synchronous rectifier is disabled when this signal is low. A

Schmitt trigger input comparator desensitizes this pin from external noise.

The IN pin is a high impedance digital input capable of accepting 3.3-V logic

level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this

pin from external noise.

Regulated 3.3-V rail. The onboard linear voltage regulator is capable of

3V3

sourcing up to 10 mA of current. Bypass with 0.22-

µF ceramic capacitance

from this pin to analog ground, AGND.

AGND

Analog ground return.

Requires a resistor to AGND for setting the current sense blanking time for

both the high-side and low-side current sense comparators. The value of this

DLY

resistor in conjunction with the resistor in series with the CS+ pin sets the high

side current sense threshold.

Output current limit threshold set pin. The output current threshold is 1/10th of

the value set on this pin. If left floating the voltage on this pin is 0.55 V. The

ILIM

voltage on the ILIM pin can range from 0.25 V to 1V to set the threshold from

25 mV to 100 mV.

Current Limit Flag. The CLF signal is a 3.3-V digital output which is latched

CLF

high after an over current event, triggered by either of the two current sense

comparators and reset after two rising edges received on the IN pin.

Sets the current sense linear amplifier “Zero” output level. The default value is

0.6 V which allows negative current measurement.

Current sense linear amplifier output. The output voltage level on this pin

represents the average output current. Any value below the level on the I0 pin

represents negative output current.

Non-inverting input of the output current sense amplifier and current limit

POS

comparator.

Inverting input of the output current sense amplifier and current limit

NEG

comparator.

Power ground return. This pin should be connected close to the source of the

PGND

low-side synchronous rectifier MOSFET.

The low-side high-current TrueDrive™ driver output. Drives the gate of the

OUT2

low-side synchronous MOSFET between PVDD and PGND.

Supply pin provides power for the output drivers. It is not connected internally

PVDD

to the VDD supply rail. The bypass capacitor for this pin should be returned to

PGND.

Floating OUT1 driver supply powered by an external Schottky diode from the

BST

PVDD pin during the synchronous MOSFET on time.

The high-side high-current TrueDrive™ driver output. Drives the gate of the

OUT1

high-side buck MOSFET between SW and BST.

I/O

OUT1 gate drive return and square wave input to output inductor.

CSBIAS

Supply pin for the high-side current sense comparator.

Non-inverting Input for the high side current sense comparator. A resistor

CS+

connected between this pin and the high side MOSFET drain, in conjunction

with the DLY resistor sets the high-side current limit threshold.

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