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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM647 датащи(PDF) 159 Page - Texas Instruments |
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TMS320DM647 датащи(HTML) 159 Page - Texas Instruments |
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159 / 166 page  www.ti.com VCLK VTXD[3:0] VRXD[3:0] 1 2 3 4 Data Data TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 Table 6-79. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-45) -720 -900 NO. PARAMETER UNIT MIN MAX 1 td(VCLKH-TXDI) Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode] 2.25 ns 1 td(VCLKH-TXDI) Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode] 0.5 ns 2 td(VCLKH-TXDV) Delay time, VCLK to VTXD[3:0] valid 6 ns Table 6-80. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-45) -720 -900 NO. UNIT MIN MAX RTM disabled 0.2 ns RTM enabled, RXD Flop = 0 1.3 ns RTM enabled, RXD Flop = 1 0.8 ns RTM enabled, RXD Flop = 2 0.4 ns Setup time, VRXD[3:0] valid before VCLK 3 tsu(RXDV-VCLKH) RTM enabled, RXD Flop = 3 0.2 ns high RTM enabled, RXD Flop = 4 0 ns RTM enabled, RXD Flop = 5 -0.3 ns RTM enabled, RXD Flop = 6 -0.5 ns RTM enabled, RXD Flop = 7 -0.7 ns RTM disabled 2 ns RTM enabled, RXD Flop = 0 0.5 ns RTM enabled, RXD Flop = 1 1.0 ns RTM enabled, RXD Flop = 2 1.5 ns 4 th(VCLKH-RXDV) Hold time, VRXD[3:0] valid after VCLK high RTM enabled, RXD Flop = 3 2.0 ns RTM enabled, RXD Flop = 4 2.5 ns RTM enabled, RXD Flop = 5 3 ns RTM enabled, RXD Flop = 6 3.5 ns RTM enabled, RXD Flop = 7 4 ns Figure 6-45. VLYNQ Transmit/Receive Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 159 |
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