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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM647 датащи(PDF) 147 Page - Texas Instruments |
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TMS320DM647 датащи(HTML) 147 Page - Texas Instruments |
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147 / 166 page  www.ti.com 6.18.3 Peripheral Register Description(s) TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals. The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as an error by an error CRC. NOTE SGMII1 is pinned out only in the DM648 device. DM647 device has only one SGMII port (SGMII0). Table 6-64 through Table 6-67 list the registers. Table 6-64. 3-port Gigabit Switch Registers HEX ADDRESS RANGE REGISTER NAME DESCRIPTION 0x02D0 3000 CPSW_Id_Ver 3pGSw ID Version Register 0x02D0 3004 CPSW_Control 3pGSw Switch Control Register 0x02D0 3008 CPSW_Soft_Reset 3pGSw Soft Reset Register 0x02D0 300C CPSW_Stat_Port_En 3pGSw Statistics Port Enable Register 0x02D0 3010 CPSW_PTYPE 3pGSw Transmit Priority Type Register 0x02D0 3014 P0_Max_Blks 3pGSw Port 0 Maximum FIFO blocks Register 0x02D0 3018 P0_BLK_CNT 3pGSw Port 0 FIFO Block Usage Count (read only) 0x02D0 301C P0_Flow_Thresh 3pGSw Port 0 Flow Control Threshold Register 0x02D0 3020 P0_Port_VLAN 3pGSw Port 0 VLAN Register 0x02D0 3024 P0_Tx_Pri_Map 3pGSw Port 0 Tx Header Pri to Switch Pri Mapping Register 0x02D0 3028 GMAC0_Gap_Thresh 3pGSw GMAC0 Short Gap Threshold Register 0x02D0 302C GMAC0_SA_LO 3pGSw GMAC0 Source Address Low Register 0x02D0 3030 GMAC0_SA_HI 3pGSw GMAC0 Source Address High Register 0x02D0 3034 P1_Max_Blks 3pGSw Port 1 Maximum FIFO blocks Register 0x02D0 3038 P1_BLK_CNT 3pGSw Port 1 FIFO Block Usage Count (read only) 0x02D0 303C P1_Flow_Thresh 3pGSw Port 1 Flow Control Threshold Register 0x02D0 3040 P1_Port_VLAN 3pGSw Port 1 VLAN Register 0x02D0 3044 P1_Tx_Pri_Map 3pGSw Port 1 Tx Header Priority to Switch Pri Mapping Register 0x02D0 3048 GMAC1_Gap_Thresh 3pGSw GMAC1 Short Gap Threshold Register 0x02D0 304C GMAC1_SA_LO 3pGSw GMAC1 Source Address Low Register 0x02D0 3050 GMAC1_SA_HI 3pGSw GMAC1 Source Address High Register 0x02D0 3054 P2_Max_Blks 3pGSw Port 2 Maximum FIFO blocks Register 0x02D0 3058 P2_BLK_CNT 3pGSw Port 2 FIFO Block Usage Count (read only) 0x02D0 305C P2_Flow_Thresh 3pGSw Port 2 Flow Control Threshold Register 0x02D0 3060 P2_Port_VLAN 3pGSw Port 2 VLAN Register 0x02D0 3064 P2_Tx_Pri_Map 3pGSw Port 2 Tx (CPDMA RX) Header Priority to Switch Pri Mapping Register 0x02D0 3068 CPDMA_Tx_Pri_Map 3pGSw CPDMA TX (Port 2 Rx) Pkt Priority to Header Priority Mapping Register 0x02D0 306C CPDMA_Rx_Ch_Map 3pGSw CPDMA RX (Port 2 Tx) Switch Priority to DMA channel Mapping Register 0x02D0 3070 - 0x02D0 307C Reserved Reserved 0x02D0 3080 GMAC0_IDVER GMAC0 ID/Version Register 0x02D0 3084 GMAC0_MacControl GMAC0 Mac Control Register 0x02D0 3088 GMAC0_MacStatus GMAC0 Mac Status Register Submit Documentation Feedback Peripheral Information and Electrical Specifications 147 |
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