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6.18.1 Ethernet Subsystem Functions

SGMII 0

GMIIport0

Gigabit

MAC 0

SGMII1

(A)

GMIIport1

AddrLookup

Engine

SGMII

Port0

HostDMA

Controller

3-port

Gigabit

Switch

Gigabit

MAC 1

Buffer

Descriptor

Memory

Configuration

Registers

REFCLK

SGMII

Port1

MII

Serial

Mgmt

Peripheral

Bus

MDIO

Configuration

Bus

Configuration

Bus

DSP

Interrupt

Controller

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

• Adaptive active equalization for superior data dependent jitter tolerance in the presence of a

lossy channel

• Loss of signal detector with programmable threshold levels in receive channels

• Integrated receiver and transmitter termination

• IEEE 802.3 gigabit Ethernet conformant

SGMII port 1 is not available on DM647.

Figure 6-42. Ethernet Subsystem Block Diagram

The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the

GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when

an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by

inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

In networking systems, packet transmission and reception are critical tasks. The communications port

programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software

and communications modules. The CPPI block in the DM648/DM647 contains 2048 words of 32-bit buffer

descriptor memory that holds up to 512 buffer descriptors.

After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet

transmit and receive operations.

• Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head

descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first

packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to

process before sending to the SGMII.

• Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head

descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the

CPPI protocol.

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