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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320C6421 датащи(PDF) 13 Page - Texas Instruments |
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TMS320C6421 датащи(HTML) 13 Page - Texas Instruments |
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13 / 227 page  www.ti.com 2.2.2 C64x+ Memory Architecture TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. The Level 1 Program memory/cache (L1P) consists of 16 KB memory space that can be configured as mapped memory or direct mapped cache. The Level 1 Data memory/cache (L1D) consists of 16 KB memory space which can be configured as mapped memory or 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 2-2 shows a memory map of the C64x+ CPU cache register for the device. Figure 2-3, shows a diagram of the C64x+ Cache Memory Architecture. Table 2-2. C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 0000 L2CFG L2 Cache configuration register L1P Size Cache configuration register (see Section 2.2.2.1, L1P 0x0184 0020 L1PCFG Configuration Register (L1PCFG) Description) 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register L1D Size Cache configuration register (see Section 2.2.2.2, L1D 0x0184 0040 L1DCFG Configuration Register (L1DCFG) Description) 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register 0x0184 0048 - 0x0184 0FFC - Reserved 0x0184 1000 EDMAWEIGHT L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - Reserved 0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - Reserved 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register 0x0184 4050 - 0x0184 4FFF - Reserved 0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback 0x0184 500C - 0x0184 5027 - Reserved 0x0184 5028 L1PINV L1P Global Invalidate 0x0184 502C - 0x0184 5039 - Reserved Submit Documentation Feedback Device Overview 13 |
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