OPA2832 datasheet(25/32 Pages) BURR-BROWN

25 / 32 page

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BOARD LAYOUT GUIDELINES

THERMAL ANALYSIS

10V

12.75mA

150W 800W

276mV

Maximum T

85°C

0.276W

100°C W

113°C

OPA3832

SBOS370 – DECEMBER 2006

A fine-scale output offset null, or dc operating point

dissipation will occur if the load requires current to be

adjustment, is often required. Numerous techniques

forced into the output at high output voltages or

are available for introducing dc offset control into an

sourced from the output at low output voltages. This

op amp circuit. Most of these techniques are based

condition puts a high current through a large internal

on adding a dc current through the feedback resistor.

voltage drop in the output transistors.

selecting

offset

trim

method,

one

key

consideration is the impact on the desired signal

path frequency response. If the signal path is

Achieving

optimum

performance

with

intended to be noninverting, the offset control is best

high-frequency amplifier such as the OPA3832

applied as an inverting summing signal to avoid

requires careful attention to board layout parasitics

interaction with the signal source. If the signal path is

and external component types. Recommendations

intended to be inverting, applying the offset control to

that will optimize performance include:

the noninverting input may be considered. Bring the

dc offsetting current into the inverting input node

a) Minimize parasitic capacitance to any ac ground

through resistor values that are much larger than the

for all of the signal I/O pins. Parasitic capacitance on

signal path resistors. This configuration ensures that

the output and inverting input pins can cause

the adjustment circuit has minimal effect on the loop

instability; on the noninverting input, it can react with

gain and thus the frequency response.

the

source

impedance

cause

unintentional

bandlimiting. To reduce unwanted capacitance, a

window around the signal I/O pins should be opened

in all of the ground and power planes around those

Maximum desired junction temperature sets the

pins. Otherwise, ground and power planes should be

maximum allowed internal power dissipation, as

unbroken elsewhere on the board.

described below. In no case should the maximum

junction temperature be allowed to exceed +150

°C.

b) Minimize the distance ( < 0.25") from the

power-supply

pins

high-frequency

0.1

µF

Operating junction temperature (TJ) is given by

decoupling capacitors. At the device pins, the ground

TA + PD × θJA. The total internal power dissipation

and power-plane layout should not be in close

(PD) is the sum of quiescent power (PDQ) and

proximity to the signal I/O pins. Avoid narrow power

additional power dissipated in the output stage (PDL)

and ground traces to minimize inductance between

to deliver load power. Quiescent power is simply the

the pins and the decoupling capacitors. Each

specified no-load supply current times the total

power-supply

connection

should

always

supply voltage across the part. PDL depends on the

decoupled with one of these capacitors. An optional

required output signal and load, though for resistive

supply decoupling capacitor (0.1

µF) across the two

loads connected to midsupply (VS/2), PDL is at a

power supplies (for bipolar operation) will improve

maximum when the output is fixed at a voltage equal

2nd-harmonic distortion performance. Larger (2.2

µF

to VS/4 or 3VS/4. Under this condition, PDL = VS

2/(4

to 6.8

µF) decoupling capacitors, effective at lower

RL), where RL includes feedback network loading.

frequency, should also be used on the main supply

Note that it is the power in the output stage, and not

pins. These may be placed somewhat farther from

into

the

load,

that

determines

internal

power

the device and may be shared among several

dissipation.

devices in the same area of the PCB.

As a worst-case example, compute the maximum TJ

c) Careful selection and placement of external

using an OPA3832 (TSSOP-14 package) in the

components will preserve the high-frequency

circuit of Figure 48 operating at the maximum

performance. Resistors should be a very low

specified ambient temperature of +85

°C and driving

reactance type. Surface-mount resistors work best

both channels at a 150

Ω load at mid-supply.

and allow a tighter overall layout. Metal film or

carbon composition axially-leaded resistors can also

provide good high-frequency performance. Again,

keep the leads and PCB traces as short as possible.

Never

use

wire-wound

type

resistors

high-frequency application. Since the output pin and

Although this value is still well below the specified

inverting input pin are the most sensitive to parasitic

maximum junction temperature, system reliability

capacitance,

always

position

the

series

output

considerations may require lower ensured junction

resistor, if any, as close as possible to the output pin.

temperatures.

The

highest

possible

internal

Other network components, such as noninverting

input termination resistors, should also be placed

close to the package.

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