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CDCL6010

SLLS780 – FEBRUARY 2007

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS

TERMINAL

NAME

PIN NO.

TYPE

DESCRIPTION

8, 11, 14,17,

20, 23, 26,

Power

1.8V digital power supply.

29, 32, 35,

38, 41

2, 5, 44, 47

Power

1.8V analog power supply.

Exposed

thermal pad

Power

Ground reference.

and pin 12

VCP, VCN

1, 48

I

External loop filter terminals.

Differential LVDS input. Single-ended 1.8V input can be dc-coupled to pin 3 with pin 4 either

CLKP, CLKN

3, 4

I

tied to pin 3 (recommended) or left open.

YP0, YN0

6, 7

YP1, YN1

9, 10

YP2, YN2

15, 16

YP3, YN3

18, 19

YP4, YN4

21, 22

10 differential CML outputs with support for jitter cleaning and clock multiplication. Support

O

YP5, YN5

27, 28

optional PLL bypass mode when jitter cleaning is not needed.

YP6, YN6

30, 31

YP7, YN7

33, 34

YP8, YN8

40, 39

YP9, YN9

43, 42

YP10, YN10

46, 45

O

Differential CML output. Straight bypass with no jitter cleaning and no clock multiplication.

SCL

24

I

SDA/SCL serial clock pin. Open drain. Always connect to a pull-up resistor.

SDA

25

I/O

SDA/SCL bidirectional serial data pin. Open drain. Always connect to a pull-up resistor.

STATUS

13

O

LVCMOS status signaling. High status indicates PLL lock.

Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed

ADD1, ADD0

37, 36

I

most significant bits (ADD[6:2]) of the 7-bit device address are 11010.

7

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