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PACKAGE (QFN24)

NC

VCC

15

14

13

RGEPACKAGE

(TOP VIEW)

CDCE421

NC

1

2

3

SDATA

4

NC

5

NC

18

NC

17

VCC

16

NC

NC

CE

NC

P0024-05

6

PIN DESCRIPTION

CDCE421

SCAS842 – APRIL 2007

The CDCE421 is also packaged in a QFN 24-pin package. The QFN package footprint is shown. Pad locations

and numbers are shown in Figure 6.

Figure 6. Pinout of the CDCE421 QFN-24 Package

Table 3 shows the pin description for the CDCE421 QFN-24 Package.

Table 3. Pinout Description of CDCE421

TERMINAL

TERMINAL

ESD

TYPE

Description

NAME

NO.

Protection

CE

1

I

Y

Chip enable

CE = 1: enable the device and the outputs.

CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z;

in LVPECL mode, LVPECLP = LVPECLN = Hi-Z.

GND

8, 9

GND

Y

Ground

No connect

2, 4–6,

Do not connect these pins. Leave them floating.

11–15,

18–20, 23,24

OUTN

7

O

Y

High-speed negative differential LVPECL or LVDS outputs. (Outputs are

enabled by CE and selected by the EEPROM configuration registers.)

OUTP

10

O

Y

High-speed positive differential LVPECL or LVDS outputs. (Outputs are

enabled by CE and selected by the EEPROM configuration registers.)

SDATA

3

I

Y

Programming pin using TI proprietary interface protocol

VCC

16, 17

Power

Y

3.3-V power supply

XIN 1

21

I

Y

In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the

other end of the crystal. In LVCMOS input single-ended driven mode, XIN1

XIN 2

22

GND

N

(pin 21) acts as input reference and XIN2 should connect to GND.

12

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