CDCL1810 datasheet(2/25 Pages) TI

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DESCRIPTION

CDCL1810

SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007

The

CDCL1810

high-performance

clock

The phase of one output group relative to the other

distributor. The programmable dividers, P0 and P1,

can be adjusted through the SDA/SCL interface. For

give a high flexibility to the ratio of the output

post-divide ratios (P0, P1) that are multiples of 5, the

frequency to the input frequency:

total number of phase adjustment steps (n) equals

the divide-ratio divided by 5. For post-divide ratios

FOUT = FIN/P

(P0, P1) that are not multiples of 5, the total number

Where:

of steps (n) is the same as the post-divide ratio. The

P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80

phase adjustment step (

∆Φ) in time units is given as:

∆Φ = 1/(n × F

OUT)

The CDCL1810 supports one differential LVDS clock

input and a total of 10 differential CML outputs. The

where FOUT is the respective output frequency.

CML outputs are compatible with LVDS receivers if

The device operates in a 1.8V supply environment

they are ac-coupled.

and is characterized for operation from –40

°C to

With careful observation of the input voltage swing

+85

°C. The CDCL1810 is available in a 48-pin QFN

and common-mode voltage limits, the CDCL1810

(RGZ) package.

can support a single-ended clock input as outlined in

the Pin Description Table.

All device settings are programmable through the

SDA/SCL, serial two-wire interface.

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