www.ti.com

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

Byte 12, Bit [6]: Power-Down Mode (except SMBus)

PD

Power-Down Mode

0

Normal Device Operation

Yes

1

(1)

Unless customer specific setting.

(2)

In power down, all PLLs and the Clock-Input-Stage are going into power-down mode, all outputs are in 3-State, all actual register

settings will be maintained and SMBus stays active. Power-Down Mode overwrites 3-State or Low-State of S0 and S1 setting in Byte 10.

Byte 13 to 18, Bit [6:0]: Outputs Switch Matrix - 6x7-Bit Divider P0-P5

DIVYx6

DIVYx5

DIVYx4

DIVYx3

DIVYx2

DIVYx1

DIVYx0

Div by

0

0

0

0

0

0

0

Not allowed

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

2

•

•

•

1

1

1

1

1

0

1

125

1

1

1

1

1

1

0

126

1

1

1

1

1

1

1

127

(1)

Unless customer specific setting.

(2)

Default setting of divider P0 = 10, P1 = 20, P2 = 8, P3 = 9, P4 = 32, and P5 = 4

Byte 19 to 24, Bit [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0-Y5

SRCYx1

SRCYx0

Yx

0

0

0

1

1

0

1

1

Yes

(1)

Unless customer specific setting.

Byte 19 to 24, Bit [2:0]: Outputs Switch Matrix (6 x 6 Switch B) Divider (P0-P5) Selection for Outputs Y0-Y5

SWBYx2

SWBYx1

SWBYx0

Any Output Yx

0

0

0

Divider P0

0

0

1

Divider P1

0

1

0

Divider P2

Y0, Y1, Y2, Y3, Y4, Y5

0

1

1

Divider P3

1

0

0

Divider P4

1

0

1

Divider P5

1

1

0

Reserved

1

1

1

Reserved

(1)

Unless customer specific setting.

Byte 19 to 24, Bit [3]: Output Y0-Y5 Enable or Low-State

ENDISYx

Output Yx

0

Disable to low

1

Enable

Yes

(1)

Unless customer specific setting.

Byte 19 to 24, Bit [6]: Output Y0-Y5 Non-Inverting/Inverting

INVYx

Output Yx Status

0

Non-inverting

Yes

1

Inverting

(1)

Unless customer specific setting.

18

Submit Documentation Feedback