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ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL RESISTANCE

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

TSSOP20

NAME

NO.

11, 12, 15,

Y0 to Y5

O

LVCMOS outputs

16, 19, 20

Dependent on SMBus settings, CLK_IN0 is the crystal oscillator input and can also be used

CLK_IN0

5

I

as LVCMOS input or as positive differential signal inputs.

Dependent on SMBus settings, CLK_IN1 is serving as the crystal oscillator output or can be

CLK_IN1

6

I/O

the second LVCMOS input or the negative differential signal input.

3, 7

Power

3.3-V power supply for the device.

14

Power

Power supply for outputs Y0, Y1.

18

Power

Power supply for outputs Y2, Y3, Y4, Y5.

GND

4, 8, 13, 17

Ground

Ground

User programmable control input S0 (PLL bypass or power-down mode) , or CLK_SEL

S0,

1

I

(selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS

CLK_SEL

inputs; internal pullup 150 k

Ω.

User programmable control input S1 (output enable/disable or all output low), dependent on

S1

2

I

the SMBus settings; LVCMOS inputs; internal pullup 150 k

Ω

SDATA

9

I/O

Serial control data input/output for SMBus controller; LVCMOS input

SCLOCK

10

I

Serial control clock input for SMBus controller; LVCMOS input

VALUE

UNIT

Supply voltage range

–0.5 to 4.6

V

V

V

±20

mA

Continuous output current

±50

mA

Storage temperature range

–65 to 150

°C

Maximum junction temperature

125

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

PARAMETER

AIRFLOW (LFM)

°C/W

0

66.3

150

59.3

θ

JA

Thermal resistance junction-to-ambient

250

56.3

500

51.9

θ

JC

Thermal resistance junction-to-case

19.7

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

4

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