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X5083PIZ датащи(PDF) 10 Page - Intersil Corporation

номер детали X5083PIZ
подробное описание детали  CPU Supervisor with 8Kbit SPI EEPROM
PDF  21 Pages
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X5083PIZ датащи(HTML) 10 Page - Intersil Corporation

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10
FN8127.3
June 15, 2006
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
•CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• When VCC is below VTRIP, communications to the device
are inhibited.
01
234
5678
9
CS
SCK
SI
SO
High Impedance
Read Instruction
(1 Byte)
Byte Address (2 Byte)
Data Out
15 14
321
0
20 21 22 23 24 25 26 27 28 29 30
765
432
10
FIGURE 5. READ OPERATION SEQUENCE
01
234
567
CS
SCK
SI
SO
Read Status
Instruction
SO = Status Reg When no Nonvolatile
Write Cycle
...
...
...
B
L
2
B
L
1
B
L
0
W
D
0
W
D
1
FIGURE 6. READ STATUS OPERATION SEQUENCE
X5083



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