SAA7215HSSLASHC2 datasheet(3/20 Pages) PHILIPS

3 / 20 page

1999 Aug 25

Philips Semiconductors

Preliminary speciﬁcation

STB5860 (Set-Top Box) STB concept

OM5730

FEATURES

1.1

SAA7219 features

1.1.1

GENERAL SAA7219 FEATURES

• Internal PR3930 32-bit RISC processor running at

81 MHz

• Comprehensive driver software and development tool

support

• A JTAG interface for board test support

• 8-kbyte 8-way set associative instruction cache

• 4-kbyte 4-way set associative instruction cache.

1.1.2

MPEG2 SYSTEMS FEATURES

• Parsing of Transport Stream (TS), Philips

Semiconductors hardware and proprietary software

data streams; maximum input rate is 108 Mbits/s

• A real time descrambler consisting of 3 modules:

– A control word bank containing 14 pairs (odd and

even) of control words and a default control word

– The Digital Video Broadcasting (DVB) descrambler

core implementing the stream decipher and block

decipher algorithms

– The MULTI2 descrambler algorithm implementing

the CBC and OFB mode descrambling functions.

• Hardware section filtering based on 32 different Packet

Identifiers (PIDs) with a flexible number of filter

conditions (8 or 4-byte condition plus 8 or 4-byte mask)

per PID and a total filter capacity of 40 (8-byte condition

checks) or up to 80 (4-byte condition checks) filter

conditions

• 4 Transport Stream/Packetized Elementary Stream

(PES) filters for retrieval of data at TS or PES level for

applications such as subtitling, TXT or retrieval of

private data

• Flexible Direct Memory Access (DMA) based storage of

the 32 section substreams and 4 TS/PES data

substreams in the external memory

• System time base management with a double counter

mechanism for clock control and discontinuity handling

2 Presentation Time Stamp (PTS)/Decoding Time

Stamp (DTS) timers

• A General Purpose/High speed (GP/HS) filter which can

serve as alternative input from e.g. IEEE 1394 devices.

It can also output either scrambled or descrambled

TS to IEEE 1394 devices.

1.1.3

EXTERNAL INTERFACE FEATURES

• A 32-bit microcontroller extension bus supporting

DRAM, SDRAM flash, (E)PROM and external memory

mapped I/O devices. It also supports a synchronous

interface to communicate with the integrated MPEG

Audio Video Graphics (AVG) decoder SAA7215 family

at 40.5 Mbytes/s.

• An IEEE 1284 interface supporting master and slave

modes; usable as a general purpose port

• 2 UART (RS232) data ports with DMA capabilities

(187.5 kbits/s) including hardware flow control RXD,

TXD, RTS and CTS for modem support

• Two dedicated smart card reader interfaces (ISO 7816

compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers supporting the

standard (100 kbits/s) and fast (400 kbits/s) I2C-bus

modes

• 32 general purpose, bidirectional I/O interface pins, 8 of

which may also be used as interrupt inputs

• 2 Pulse Width Modulated (PWM) outputs with 8-bit

resolution.

1.2

SAA7215 family features

1.2.1

GENERAL SAA7215 FAMILY FEATURES

• Single or double external synchronous DRAM organized

as 1M

× 16 or 2 × 1M × 16 interfacing at 81 MHz. Due to

efficient memory use in MPEG decoding, more than

1 Mbit is available for graphics in the single SDRAM

configuration whereas 17 Mbits are available in the

double SDRAM configuration targeted to BSkyB 3.00

and Canal+ 4.0 specifications.

• Dedicated input for compressed audio and video in PES

or ES in byte wide or bit serial format; accompanying

strobe signals distinguish between audio and video data

• Optimum compatibility with SAA7219 TMIPS controller

• Flexible memory allocation under control of the external

Central Processing Unit (CPU) enables optimized

partitioning of memory for different tasks

• Boundary scan testing implemented.

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