MBM29F400TC datasheet(21/48 Pages) SPANSION

21 / 48 page

MBM29F400TC-55/-70-90/MBM29F400BC-55/-70-90

RESET

Hardware Reset

The MBM29F400TC/BC device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode 20

µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

device requires time of tRH before it will allow read access. When the RESET pin is low, the device will be in the

standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset

occurs during a program or erase operation, the data at that particular location will be corrupted. Please note

that the RY/BY output signal should be ignored during the RESET pulse. Refer to “RESET/RY/BY Timing

Diagram” in sTIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional

functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)

cannot be used.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F400TC/BC device. When this

pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ15 to

DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ7 to DQ0 and the DQ15 to DQ8 bits are ignored. Refer

to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE

Timing Diagram for Write Operations” in sTIMING DIAGRAM for the timing diagram.

Data Protection

The MBM29F400TC/BC are designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the device automatically

resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and

power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above 3.2 V.

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

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