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IRCC2.0 датащи(PDF) 1 Page - SMSC Corporation

номер детали IRCC2.0
подробное описание детали  Infrared Communications Controller
PDF  87 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

IRCC2.0 датащи(HTML) 1 Page - SMSC Corporation

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IrCC 2.0
PRELIMINARY
Infrared Communications Controller
FEATURES
•
Multi-Protocol Serial Communications
Controller
•
Full IrDA v1.1 Implementation: 2.4 kbps -
115.2 kbps, 0.576 Mbps, 1.152 Mbps and 4
Mbps
•
Consumer Infrared (Remote Control)
Interface
•
SHARP Amplitude Shift Keyed Infrared
(ASK IR) Interface
•
Direct Rx/Tx Infrared Diode Control (Raw)
and General Purpose Data Pins
•
Programmable High-Speed Synchronous
Communications Engine (SCE) with a 128-
Byte FIFO and Programmable Threshold
•
Programmable DMA Refresh Counter
•
High-Speed NS16C550A-Compatible
Universal Asynchronous Receiver/
Transmitter Interface (ACE UART) with 16-
Byte Send and Receive FIFOs
•
ISA Single-Byte and Burst-Mode DMA and
Interrupt-Driven Programmed I/O with Zero
Wait State and String Move Timing
•
16 Bit CRC-CCITT and 32 Bit IEEE 802
CRC32 Hardware CRC Generators
•
Automatic Transceiver Control
•
Transmit Pulse Width Limiter
•
SCE Transmit Delay Timer
•
IR Media Busy Indicator
GENERAL DESCRIPTION
This
document
describes
the
Infrared
Communications Controller (IrCC 2.0) function,
which is common to a number of SMSC
products.
The IrCC 2.0 consists of two main
architectural blocks: the ACE 16C550A UART
and a Synchronous Communications Engine
(SCE) (Figure 2).
It’s own unique register set
supports each block.
The IrCC 2.0 UART-driven IrDA SIR and SHARP
ASK
modes
are
backward
compatible
with current SMSC Super I/O and Ultra I/O
infrared implementations.
The IrCC 2.0 SCE
supports IrDA v1.1 0.576 Mbps, 1.152 Mbps, 4
Mbps, and Consumer IR modes. All of the SCE-
driven modes can use DMA. The IrCC 2.0 offers
flexible signal routing and programmable output
control through the Raw mode interface, General
Purpose Data pins and Output Multiplexer. Chip-
level address decoding is required to access the
IrCC 2.0 register sets.


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