9

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FIGURE 15. DEAD TIME

FIGURE 16. UNDERVOLTAGE THRESHOLD

-60

-40

-20

0

20

40

60

80

100

120

140

160

0

2

4

6

RDEL = 100k

Ω

RDEL = 10k

Ω

-60

-40

-20

0

20

40

60

80

100

120

140

160

6

6.5

7

7.5

8

8.5

9

9.5

10

10.5

11

ENABLE (50K, UVLO TO GND)

TRIP (50K, UVLO TO GND)

ENABLE (UVLO OPEN)

TRIP (UVLO OPEN)

-60

-40

-20

0

20

40

60

80

100

120

140

160

10

15

20

25

HIP4086