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AM29BDS320G датащи(PDF) 49 Page - SPANSION

номер детали AM29BDS320G
подробное описание детали  32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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AM29BDS320G датащи(HTML) 49 Page - SPANSION

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October 1, 2003 27243B1
Am29BDS320G
47
Prelimin ary
AC Characteristics
Synchronous/Burst Read
Note:
Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
D8
(54 MHz)
D3
(54 MHz)
C8
(40 MHz)
C3
(40 MHz) Unit
JEDEC Standard
tIACC
Latency (Even Address in Reduced
Wait-State Handshaking Mode)
Max
87.5
95
ns
Parameter
Description
D8, D9
(54 MHz)
D3, D4
(54 MHz)
C8, C9
(40 MHz)
C3, C4
(40 MHz) Unit
JEDEC Standard
tIACC
Latency—(Standard Handshaking or
Odd Address in Handshake mode)
Max
106
120
ns
tBACC
Burst Access Time Valid Clock to
Output Delay
Max
13.5
20
ns
tACS
Address Setup Time to CLK (Note
Note:)
Min
5
ns
tACH
Address Hold Time from CLK (Note
Note:)
Min
7
ns
tBDH
Data Hold Time from Next Clock Cycle
Min
3
ns
tOE
Output Enable to Output Valid
Max
13.5
20
ns
tCEZ
Chip Enable to High Z
Max
10
10.5
10
10.5
ns
tOEZ
Output Enable to High Z
Max
10
10.5
10
10.5
ns
tCES
CE# Setup Time to CLK
Min
5
ns
tRDYS
RDY Setup Time to CLK
Min
5
4.5
5
4.5
ns
tRACC
Ready Access Time from CLK
Max
13.5
14
20
20
ns
tAAS
Address Setup Time to AVD# (Note
Note:)
Min
5
ns
tAAH
Address Hold Time to AVD# (Note
Note:)
Min
7
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
tAVC
AVD# Low to CLK
Min
5
ns
tAVD
AVD# Pulse
Min
12
ns
tACC
Access Time
Max
70
ns



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