15

HIP4080

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1 BHB

HEN

DIS

OUT

IN+

HDEL

IN-

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

100K

RDEL

RDEL

0.1

µF

2N3906

ENABLE

56K

8.2V

56K

100K

FIGURE 32.

DIS

LDEL

=10ms

t1

t2

8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)

12V, FINAL VALUE

5.1V

NOTES:

2. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If

the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+

and IN- pins must cycle at least once.

3. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry.

FIGURE 33. TIMING DIAGRAM FOR FIGURE 32

HIP4080