TPS25751D datasheet(67/89 Pages) TI1

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9.4.2 TPS25751S - Layout

9.4.2.1 Layout Guidelines

Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation

from the power paths. The combination of power and high speed data signals are easily routed if the following

guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing capabilities.

9.4.2.1.1 Recommended Via Size

Proper via stitching is recommended to carrying current for the VBUS power paths and grounding. The

recommended minimum via size is shown below, but larger vias are an option for low density PCB designs.

A single via is capable of carrying 1A, verify the tolerance with the board manufacturing. Vias are recommended

to be tented when located close to the PD controller.

16mil

8mil

Figure 9-33. Recommend Minimum Via Size

9.4.2.1.2 Minimum Trace Widths

Below are the minimum trace widths for analog and digital pins. The trace width limitations are also defined by

the board manufacturing process used. Consult with manufacturing for determining the minimum trace widths

and tolerance.

Table 9-5. Minimum Trace Width

Route

Minimum Width (mils)

CC1, CC2

VIN_3V3, LDO

Component GND

GPIO

9.4.2.2 Layout Example

9.4.2.2.1 TPS25751S Schematic Layout Example

Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All

I/O are fanned out to provide an example for routing out all pins, not all designs utilize all of the I/O on the

TPS25751S.

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TPS25751

SLVSH93 – OCTOBER 2023

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