5-84

NOTES:

1. The holding register is loaded on the trailing edge of TBRL.

FIGURE 7. TRANSMITTER TIMING WAVEFORMS

TRC

TBRL

TRO

TBRE

TRE

T BUS 0

T BUS 7

12

DATA

1ST DATA BIT

TRANSMITTER SHIFT

REGISTER LOADED

(NOTE 2)

TRANSMITTER BUFFER

REGISTER LOADED

(NOTE 1)

3

4

56

7

14

15

16

1

23

NOTES:

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding

register, the OE signal will come true.

FIGURE 8. RECEIVER TIMING WAVEFORMS

RRC

R BUS 7

DR

DRR

12

START BIT PARITY

CLOCK 7 1/2

SAMPLE

34

5

6

7

16

(NOTE 1)

RRI

12

34

5

6

78

9

STOP BIT 1

CLOCK 7 1/2 LOAD

HOLDING REGISTER

DATA

R BUS 0 -

OE

PE

(NOTE 2)

FE

CDP6402, CDP6402C