AAT3258

300mA LDO Linear Regulator with µP Reset

2

3258.2006.03.1.6

Pin Descriptions

Pin Configuration

TSOPJW-8

(Top View)

1

2

3

4

8

7

6

5

VIN

SHDN

VDET

MR

OUT

BYP

GND

RESET

Pin #

Symbol

Function

1

VIN

LDO voltage regulator input pin. This pin should be decoupled with 1µF or

greater capacitor. See application information.

2

SHDN

LDO voltage regulator shutdown pin. This pin should not be left floating.

When connected low, all the internal circuitry is powered down. When high, it

is in normal operation.

3

VDET

Microprocessor reset input power supply pin. It may be connected to V

4

MR

Manual reset active low input. A logic low signal on MR asserts a reset condi-

tion. Asserted reset continues as long as MR is low and for a minimum of

150ms after MR returns high.

5

RESET

Reset output remains low while V

so for a minimum of 150ms after V

6

GND

Ground connection pin.

7

BYP

LDO voltage regulator bypass capacitor connection. To improve AC ripple

rejection and decrease LDO regulator self noise, connect a 10nF ceramic

capacitor between this pin and GND.

8

OUT

LDO voltage regulator output pin; should be decoupled with a 2.2µF or

greater value low ESR ceramic capacitor.