LD7537

10

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7537-DS-01a December 2011

Fig. 15

A 230nS leading-edge blanking (LEB) time is included in

the input of CS pin to prevent the false-trigger from the

current spike. In the low power applications, if the total

pulse width of the turn-on spikes is less than 230nS and

the negative spike on the CS pin below -0.3V, the R-C

filter is free to eliminate. (As shown in Fig.16).

However, the total pulse width of the turn-on spike is

determined according to output power, circuit design and

PCB layout.

It is strongly recommended to adopt a

smaller R-C filter (as shown in Fig. 17) for larger power

application to avoid the CS pin being damaged by the

negative turn-on spike.

Output Stage and Maximum Duty-Cycle

An output stage of a CMOS buffer, with typical 300mA

driving capability, is incorporated to drive a power

MOSFET directly.

And the maximum duty-cycle of

LD7537 is limited to 75% to avoid the transformer

saturation.

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431 at

the secondary side through the photo-coupler to the

COMP pin of the LD7537.

Similar to UC3842, the

LD7537 would carry a diode voltage offset at the stage to

feed the voltage divider at the ratio of RA and RB, that is,

)

V

V

(

RB

RA

RB

V

F

COMP

)

PWM

(

COMPARATOR

−

×

+

=

−

A pull-high resistor is embedded internally and can be

eliminated externally.

Fig. 16

Fig. 17

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