LD7530 datasheet(10/19 Pages) LEADTREND

10 / 19 page

LD7530/LD7530A

Leadtrend Technology Corporation

LD7530&LD7530A-DS-04 December 2007

Fig. 15

A 200nS leading-edge blanking (LEB) time is included in the

input of CS pin to prevent the false-trigger from the current

spike. In the low power application, if the total pulse width of

the turn-on spikes is less than 200nS and the negative spike

on the CS pin doesn’t exceed -0.3V, it could eliminated the

R-C filter (as shown in the figure16).

However, the total pulse width of the turn-on spike is

decided by the output power, circuit design and PCB layout.

It is strongly recommended to adopt a smaller R-C filter (as

shown in figure 17) for higher power application to avoid the

CS pin being damaged by the negative turn-on spike.

Output Stage and Maximum Duty-Cycle

An output stage of a CMOS buffer, with typical 300mA

driving capability, is incorporated to drive a power MOSFET

directly. And the maximum duty-cycle of LD7530/LD7530A

is limited to 75% to avoid the transformer saturation.

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431 at

the secondary side through the photo-coupler to the COMP

pin of the LD7530/LD7530A.

Similar to UC3842, the

LD7530/LD7530A would carry 2 diodes voltage offset at the

stage to feed the voltage divider at the ratio of 1/3, that is,

)

(

)

(

COMP

PWM

COMPARATOR

−

A pull-high resistor is embedded internally and can be

eliminated externally.

Fig. 16

Fig. 17

Oscillator and Switching Frequency

The switching frequency of LD7530/LD7530A is fixed as 65

KHz internally to provide the optimized operations by

considering the EMI performance, thermal treatment,

component sizes and transformer design.

LD7530 датащи(PDF) 10 Page - Leadtrend Technology

LD7530 датащи(HTML) 10 Page - Leadtrend Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL