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DSP56F803 датащи(PDF) 36 Page - Freescale Semiconductor, Inc |
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DSP56F803 датащи(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 57 page ![]() External Bus Asynchronous Timing 56F803 Technical Data, Rev. 16 Freescale Semiconductor 31 Input Data Hold to RD Deasserted tDRD 0— ns RD Assertion Width Wait states = 0 Wait states > 0 tRD 19 (T*WS) + 19 — — ns ns Address Valid to Input Data Valid Wait states = 0 Wait states > 0 tAD — — 1 (T*WS) + 1 ns ns Address Valid to RD Asserted tARDA -4.4 — ns RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 tRDD — — 2.4 (T*WS) + 2.4 ns ns WR Deasserted to RD Asserted tWRRD 6.8 — ns RD Deasserted to RD Asserted tRDRD 0— ns WR Deasserted to WR Asserted tWRWR 14.1 — ns RD Deasserted to WR Asserted tRDWR 12.8 — ns Table 3-10 External Bus Asynchronous Timing1, 2 (Continued) Operating Conditions: V SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Max Unit |
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