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ADP1870-0.3-EVALZ датащи(PDF) 7 Page - Cirrus Logic

номер детали ADP1870-0.3-EVALZ
подробное описание детали  Evaluation Kit
PDF  10 Pages
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производитель  APEX [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo APEX - Cirrus Logic

ADP1870-0.3-EVALZ датащи(HTML) 7 Page - Cirrus Logic

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EK76
EK76U Rev A
7
CURRENT SENSE
The optional current sense gain and offset circuit is designed to interface with various ADCs in closed-
loop current/torque control. Follow the below schematic and equations to determine the proper component
values.
After assembly of the EK76 including the above Current Sense circuit, R22 must be trimmed to reach the
desired value of VOS. To do this, attach a Voltmeter to measure the voltage between pins 11 (negative) and
13 (positive) of P2. Apply the low-voltage supply VCC (+VS should NOT be active). Adjust R22 until the desired
value for VOS is shown on the Voltmeter.
The following equation represents the Low-Side Phase Current (IPHASE) as a function of voltage measured
at IM_X (VM):
Value
Applicable Designators on
EVAL94
Equation
Default
Value
Units
Suggested
Tolerance
VOS
Bias
ADC min input (or higher)
1.65
V
-
VOUT_MAX -
ADC max input (or lower)
3.3
V
-
IOUT_MAX
-
< 80 A
33
A
-
Gain
-
(VOUT_MAX-VOS) / (IOUT_MAX*
10 mΩ)
5
V/V
-
RF
R9, 12, 13, 16, 17, 20
1.8k < RF < 100k
50k
Ω
0.1%
RIN
R10, 11, 14, 15, 18, 19
RF / Gain
10k
Ω
0.1%
RT
R22 (potentiometer)
1k < RT < 100k
10k
Ω
-
RL
R21
Roughly RT ((VCC/2VOS) – 1)
39k
Ω
-
C4
C4
C4 = 100n
100n
F
X7R
fFIL
-
Typically 200k < fFIL < 1M
Hz
-
RFIL
R23, 24, 25
Typically 100 < RFIL < 1k
0
Ω
-
CFIL
C1, 2, 3
1 / (2π * fFIL * RFIL)
0
F
-
R1-3
10
RIN
RIN
+
-
RF
RF
BIAS
RFIL
CFIL
IM_X
PGND_X
3X
+
-
1X
BIAS
RL
RT
VCC
C4
PGND
DGND
DGND
Phase
Current
IPHASE
VM VOS
Gain 0.01
---------------------------------
=



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