ST7538Q datasheet(18/44 Pages) STMICROELECTRONICS

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Functional description

ST7538Q

18/44

In Data Reception Mode:

–

Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q

(CLR/T line) rising edge, value on FSK Demodulator is read and put to the data

reception line (RxD line). ST7538Q recovers the bit timing according to the

BaudRate Selected.

–

Asynchronous Mains access: Value on FSK Demodulator is sent directly to the

data reception line (RxD line). The Host Controller recovers the communication

timing (CLR/T line should be neglected).

5.5

Host processor interface

ST7538Q exchanges data with the host processor through a serial interface.

The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged

using RxD, TxD and CLR/T lines.

Four are the ST7538Q working modes:

●

Data Reception

●

Data Transmission

●

Control Register Read

●

Control Register Write

REG_DATA and RxTx lines are level sensitive inputs.

ST7538Q features two type of Host Communication Interfaces:

–SPI

–UART

The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI

interface is selected while if UART/SPI pin is forced to “1” UART interface is selected (a). The

type of interface affects the Data Reception by setting the idle state of RxD line. When

ST7538Q is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available

on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the

RxD line is forced to “0” when UART/SPI pin is forced to ”0” or to “1” when UART/SPI pin is

forced to ”1”.

Table 8. Data and control register access bits configuration

REG_DATA

RxTx

Data Transmission

Data Reception

Control Register Read

Control Register Write

UART Interface Mode modifies also Control Register Functions and provides one more level of Rx sensitivity

(see par. 5.11)

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