9

SY10E196

SY100E196

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

asserted to signal the need to cascade the delay to the

pin of chip #2 will be de-asserted and the delay will be

other hand, will have its SET MAX pin asserted, resulting

address bus.

will be set.

In addition, to maintain monotonicity, an

additional gate delay is selected in the cascade circuitry.

increases from 31.75 gates to 32 gates. A 32-gate delay

is the maximum delay setting for the E196.

When cascading multiple PDCs, it will prove more cost-

effective to use a single E196 for the MSB of the chain,

while using E195 for the lower order bits. This is due to

the fact that only one fine tune input is needed to further

reduce the delay step resolution.