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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UJA1069TW датащи(PDF) 13 Page - NXP Semiconductors |
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UJA1069TW датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 64 page  UJA1069_2 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 — 5 March 2007 13 of 64 NXP Semiconductors UJA1069 LIN fail-safe system basis chip Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register. This enables an easy software flow control with defined watchdog behavior when switching between different software modules. 6.4.1 Watchdog start-up behavior Following any reset event the watchdog is used to monitor the ECU start-up procedure. It observes the behavior of the RSTN pin for any clamping condition or interrupted reset wire. In case the watchdog is not properly served within tWD(init), another reset is forced and the monitoring procedure is restarted. In case the watchdog is again not properly served, the system enters Fail-safe mode (see also Figure 4, Start-up mode and Restart mode). 6.4.2 Watchdog window behavior Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated. This ensures that the microcontroller operates within the required speed; a too fast as well as a too slow operation will be detected. Watchdog triggering using the Window mode is illustrated in Figure 5. The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any too early or too late watchdog access or wrong Mode register code access will result in an immediate system reset, entering Start-up mode. Fig 5. Watchdog triggering using Window mode mce626 trigger window trigger window too early trigger restarts period 50 % trigger via SPI trigger via SPI last trigger point earliest possible trigger point latest possible trigger point earliest possible trigger point latest possible trigger point too early trigger restarts period (with different duration if desired) period 100 % 50 % 100 % new period |
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