AT43USB355M-AC datasheet(89/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

Function End-point 0..3 Control and Acknowledge Register – FCAR0..3

• Bit 7 – Reserved

This bit is reserved in the AT43USB355 and will read as zero.

• Bit 6 – DATA END

When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last

data packet in FIFO, or that the microcontroller has processed the last data packet it expects

from the Host.

• Bit 5 – FORCE STALL

This bit is set by the microcontroller to indicate a stalled end-point. The hardware will send a

STALL handshake as a response to the next IN or OUT token. The microcontroller sets this bit

if it wants to force a STALL. A STALL is send if the host continues to ask for data after the data

is exhausted.

• Bit 4 – TX PACKET RDY: Transmit Packet Ready

When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a

packet of data. This bit is cleared by the hardware after the USB Host acknowledges the

packet. For ISO end-points, this bit is cleared unconditionally after the data is sent.

The microcontroller should write into the FIFO only if this bit is cleared. After it has completed

writing the data, it should set this bit. This data can be of zero length.

The hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX

Complete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to

the microcontroller.

• Bit 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt

Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is

not actually stored and thus does not have to be cleared.

• Bit 2 – Reserved

This bit is reserved in the AT43USB355 and will read as zero.

• Bit 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt

Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit

is not actually stored and thus does not have to be cleared.

• Bit 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt

Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is

not actually stored and thus does not have to be cleared.

Bit

Function EP1 $1FA4

–

DATA

END

FORCE

STALL

TX PACKET

RDY

STALL_SENT-

ACK

–

RX_OUT_PACKET

_ACK

TX_COMPLETE

_ACK

FCAR1

Function EP2 $1FA3

–

DATA

END

FORCE

STALL

TX PACKET

RDY

STALL_SENT-

ACK

–

RX_OUT_PACKET

_ACK

TX_COMPLETE

-ACK

FCAR2

Function EP3 $1FA2

–

DATA

END

FORCE

STALL

TX PACKET

RDY

STALL_SENT-

ACK

–

RX_OUT_PACKET

_ACK

TX_COMPLETE

-ACK

FCAR3

Read/Write

R/W

Initial Value

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