AT43USB355 datasheet(51/115 Pages) ATMEL

51 / 115 page

AT43USB355

2603G–USB–04/06

(CS12..CS10 = 001 or 000), the PWM output goes active when the counter reaches the TOP

value, but the down-counting compare match is not interpreted to be reached before the next

time the counter reaches the TOP value, making a one-period PWM pulse.

Note:

X = A or B

In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from

$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is

executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are

enabled. This also applies to the Timer Output Compare1 flags and interrupts.

Watchdog Timer

The Watchdog Timer is clocked from a 1 MHz clock derived from the 6 MHz on chip oscillator.

By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted,

see Table 18 for a detailed description. The WDR (Watchdog Reset) instruction resets the

Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset

period. If the reset period expires without another Watchdog reset, the AT43USB355 resets

and executes from the reset vector.

To prevent unintentional disabling of the watchdog, a special turn-off sequence must be fol-

lowed when the watchdog is disabled. Refer to the description of the Watchdog Timer Control

Figure 17. Watchdog Timer

Table 17. PWM Outputs OCR1X = $0000 or Top

COM1X1

COM1X0

OCR1X

Output OC1X

$0000

TOP

$0000

TOP

1 MHz Clock

MCU Reset

WDE

WDP2

WDP1

WDP0

Watchdog

Reset

Watchdog Prescaler

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