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ATMEGA88 датащи(PDF) 39 Page - ATMEL Corporation |
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ATMEGA88 датащи(HTML) 39 Page - ATMEL Corporation |
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39 / 374 page ![]() 39 2545J–AVR–12/06 ATmega48/88/168 8. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. 8.1 Sleep Modes Figure 7-1 on page 27 presents the different clock systems in the ATmega48/88/168, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 8-1 shows the different sleep modes and their wake up sources. Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2. If Timer/Counter2 is running in asynchronous mode. 3. For INT1 and INT0, only level interrupt. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction. See Table 8-2 on page 43 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8.2 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk CPU and clkFLASH, while allowing the other clocks to run. Table 8-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators Wake-up Sources Sleep Mode Idle X X X X X(2) XX X X X X X ADC Noise Reduction XX X X(2) X(3) XX(2) XX X Power-down X(3) XX Power-save X X(2) X(3) XX X Standby(1) XX(3) XX |
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